This set of MCQ(multiple choice questions) focuses on the Introduction to Operating System Week 6 Answers
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Course layout
Week 1: Assignment solutions
Week 2: Assignment solutions
Week 3: Assignment solutions
Week 4: Assignment solutions
Week 5: Assignment Solutions
Week 6: Assignment solutions
Week 7: Assignment solutions
Week 8: Assignment solutions
Week 9: Assignment solutions
Week 10: Assignment solutions
Week 11: Assignment solutions
Week 12: Assignment solutions
NOTE: You can check your answer immediately by clicking show answer button. Moreover, this set of Introduction to Operating System Week 6 Answers” contains 10 questions.
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Introduction to Operating System Week 6 Answers
Q1. Consider the following statements:
i) if(count==0)
ii) add %eax,%ebx
a) i is atomic , ii is non-atomic
b) i is non-atomic , ii is non-atomic
c) i is non-atomic , ii is atomic
d) Both are atomic
Answer: c) i is non-atomic , ii is atomic
Q2. Which of the following condition could occur due to lack of synchronization?
a) Inconsistency
b) Loss of data
c) Deadlock
d) All of these
Answer: d) All of these
Q3. Return value of xchg instruction is_____________
a) Old value
b) New value
c) 1 if operation succeeds and 0 if operation fails
d) None of the above
Answer: a) Old value
Q4. By using intel hardware xchg instruction, ensures that
1. The critical section is deadlock free
2. Solution is starvation free
3. Process enters CS in FIFO order
4. More than one process enters critical section at same time
Which of the above statement is TRUE?
a) a only
b) a and b
c) b and c
d) d only
Answer: a) a only
Q5. Your friend wants to design synchronization primitives and tells you that he would be better off by strictly ensuring that the processes alternate the critical section. Your response would be:
a) That might not satisfy the “progress” requirement
b) That might not satisfy the “mutual exclusion” requirement
c) That might not satisfy the “bounded wait” requirement
d) I guess that would suffice.
Answer: a) That might not satisfy the “progress” requirement
Q6. State True/False
Bakery algorithm ensures that no process is starved.
a) True
b) False
Answer: a) True
Q7. State True/ False
Message passing is slow compared to shared memory and more error prone.
a) True
b) False
Answer: b) False
Q8. Inter process communication with message passing, the shared memory is in
a) User space
b) Kernel space
c) Virtual memory
d) None of these
Answer: b) Kernel space
Q9. In a certain application, the initial value of a counting semaphore s is 10. The following operations were completed on the semaphore in the given order 5P, 20P, 2V, 18P, 5V, 10P, 1V. The new value of counting semaphore is _____________ ?
Answer: -35
Q10. If the value of a counting semaphore s = 4, then the maximum number of requests for the critical section before it blocks is _____________ ?
a) 0
b) 1
c) 2
d) 4
Answer: d) 4
Q11. State True/False
It is possible to share the messages even without attaching the shared memory with the address space of calling process.
a) True
b) False
Answer: b) False
Q12. The variable turn can have values 0 or 1
Void Process (i)
{
while(1)
{
//Non-critical section
While (turn!=i);
// Critical section
turn = j;
}
}The above code does not provide
a) Mutual exclusion
b) Progress
c) Bounded wait
d) None of these
Answer: c) Bounded wait
Q13. Test and Set instruction, which provides hardware synchronization does not guarantee __________.
a) Mutual exclusion
b) Progress
c) Bounded wait
d) None of these
Answer: b) Progress
Q14. Peterson’s solution is a synchronization mechanism for maximum of _____________ processes.
Answer: 2
Q15. Atomic operations like test & set ensure that
a) They are executed in a single cycle
b) They can be executed in multiple cycles,no other memory instruction is executed while this instruction is executing
c) They can be executed in multiple cycles,but no other memory instruction to the same variable is executed while this instruction is executing
d) No other instructions execute in the background while this instruction is being executed
Answer: c) They can be executed in multiple cycles,but no other memory instruction to the same variable is executed while this instruction is executing
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