Advanced Computer Architecture | NPTEL 2022 | Week 0 Assignment Solutions

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Advanced Computer Architecture NPTEL 2022 Week 0 Assignment Solutions

Q1. Which of the following is connected to a bidirectional data bus inside a processor?

a) MAR
b) PC
c) IR
d) MDR

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Q2. Which of the following is also known as Load-store architecture?

a) Stack architecture
b) Accumulator architecture
c) Register-Memory architecture
d) Register-Register

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Q3. In a MIPS RISC 5-stage  instruction pipeline, for a LOAD instruction the EXE stage:

a) Performs data transfer from the addressed memory location to the register
b) Read the address from the base register
c) Compute the effective address from base register and displacement
d) Write the result to destination register

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Q4. In a 5 stage RISC instruction pipeline, reading data from register file happens in:

a) ID stage
b) WB stage
c) MEM stage
d) IF stage

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Q5. A cache memory has 64 KB capacity, 64 byte block size and is 4-way set associative. The number of sets in the cache is _____

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Advanced Computer Architecture NPTEL week 0 Assignment Solutions

Q6. For a 16KB, 4-way associative cache with block size 16 bytes, what is the number of tag bits per block if the physical address capacity is 16MB?

a) 20 bit
b) 18 bit
c) 16 bit
d) 12 bit

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Q7. If a 32 bit value (0x77662244) is stored in memory addresses 2000, 2001, 2002 and 2003 in little endian format, then location 2001 holds the value 

a) 0x77
b) 0x66
c) 0x22
d) 0x44

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Q8. A cache has hit rate of 90%, hit latency of 2 cycles and miss penalty of 20 cycles. The average memory access time is _____ cycles.

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Advanced Computer Architecture NPTEL week 0 Assignment Solutions

Q9. During an instruction fetch operation

a) Contents of MAR gets copied to PC.
b) Contents of PC gets copied to MDR.
c) Contents of MAR gets copied to IR.
d) Contents of PC gets copied to MAR.

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Q10. Which all stages in a 5-stage RISC-MIPS instruction pipeline access the cache memory?

a) IF only
b) IF and ID
c) IF and MEM
d) MEM only

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Advanced Computer Architecture NPTEL week 0 Assignment Solutions

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