Advanced Computer Architecture | NPTEL 2022 | Week 1 Assignment Solutions

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Advanced Computer Architecture NPTEL 2022 Week 1 Assignment Solutions

Q1. Which one of the following MIPS pipeline stages calculates effective address (EA) for a STORE instruction?

a) Instruction Fetch
b) Instruction Decode
c) Execute
d) Memory Access

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Q2. Which of the following statements is FALSE with respect to fetching operations?

a) Contents of MAR are transferred to the address bus.
b) Contents of MDR are transferred to IR.
c) Instruction is transferred from the memory to the PC.
d) Contents of PC are transferred to MAR.

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Q3. Which one of the following is not a SPEC 2006 floating-point benchmark?

a) wrf
b) astar
c) soplex
d) namd

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Q4. An instruction pipeline was designed with five stages. Individually each stage will take 2.9 ns, 2.7 ns, 4.3 ns, 3.1 ns, and 3.2 ns, respectively. The pipeline latch latency is 0.3 ns. What is the minimum cycle time of the pipeline?

a) 16.2 ns
b) 4.3 ns
c) 4.6 ns
d) 16.5 ns

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Q5. Which one of the following Special purpose register holds the operation code of the currently executing instruction?

a) Stack Pointer
b) Program Counter
c) Base Register
d) Instruction Register

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Advanced Computer Architecture NPTEL week 1 Assignment Solutions

Q6. The 8-bit hexadecimal values 0x08, 0x07, 0x06, and 0x05 are stored in memory addresses 5000, 5001, 5002, and 5003, respectively. A processor that follows a little-endian format reads a 32-bit word from the memory location 5000. What is the value that is read by the processor?

a) 0x05060708
b) 0x08080808
c) 0x08070605
d) 0x05050505

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Q7. Which one of the following is also known as Load-Store architecture?

a) Stack Architecture
b) Register-Register Architecture
c) Register-Memory Architecture
d) Accumulator Architecture

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Advanced Computer Architecture NPTEL week 1 Assignment Solutions

Q8. A 32:2³² decoder is connected to the memory address bus of a processor. Assume word length is 1 byte. What can be the capacity of the memory to which the decoder is connected?

a) 32 KB
b) 4 MB
c) 64 KB
d) 4 GB

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Advanced Computer Architecture NPTEL week 1 Assignment Solutions

Q9. Which one of the following statements is FALSE with respect to the instruction pipeline?

a) Pipelining can increase the throughput of a system.
b) Pipelining partitions the system into multiple independent stages with buffers placed between the stages
c) Pipelining reduces the latency of each individual instruction.
d) Unbalanced lengths of pipeline stages reduces overall speedup.

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Q10. A new multimedia unit (MU) that is added to a processor speeds up the completion of multimedia instructions given to the processor by 5 times. Assuming a program has 30% multimedia instructions, what is the overall speedup gained while running the program when it is executed on the processor with the new MU than when it is run on the processor without this MU?

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Advanced Computer Architecture NPTEL week 1 Assignment Solutions

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